The present invention relates to a phase-locked loop circuit, specifically relates to a digital phase-locked loop circuit of which the main components are composed of a digital circuit. The present invention further relates to a communication apparatus which employs the phase-locked loop circuit.
A phase-locked loop circuit (PLL circuit) is employed as a reference signal source of a radio frequency integrated circuit (RF-IC). In recent years, development of an all digital PLL circuit (ADPLL circuit) in which all the passive elements of a PLL circuit are replaced with a digital circuit is advancing. In employing a PLL circuit for wireless terminals, such as a mobile-phone and a wireless local area network (WLAN), low power consumption becomes an important factor which determines worth of the product. As a PLL circuit which is able to operate with low power consumption, technology described in the following patent documents is known, for example.
Japanese Unexamined Patent Publication No. 2008-160594 (hereinafter referred to as Patent Document 1) discloses an ADPLL circuit which employs a time-to-digital converter (TDC). The time-to-digital converter disclosed by Patent Document 1 is provided with a switching element for changing the number of stages of delay circuits in operation corresponding to an input frequency, with the use of a frequency control signal which controls an oscillating frequency. Since only the delay circuits of a required number of stages operate corresponding to a cycle of the input frequency, the present time-to-digital converter can support an operation in a wide-band frequency range, in addition, it can attain low power consumption of the entire system, especially at a high input frequency.
A PLL circuit disclosed by Japanese Unexamined Patent Publication No. Hei 11(1999)-127062 (hereinafter referred to as Patent Document 2) has a phase comparator circuit which compares a phase of a reference clock obtained by dividing a supplied clock with a divider and a phase of a variable clock. The phase comparator circuit lowers the frequency of operation of own circuit by increasing a dividing ratio of the divider, when it is detected that the phases of both clocks are in agreement. Accordingly, the power consumption of the PLL circuit can be reduced. At the time of reset which returns the state from the non-active state to the active state, the frequency of operation of the phase comparator circuit returns to the original high state by setting the dividing ratio of the divider to the original low value. Therefore, time required for phase synchronization of both clocks can be shortened.
A digital PLL circuit disclosed by Japanese Unexamined Patent Publication No. Hei 10(1998)-070456 (hereinafter referred to as Patent Document 3) is provided with a circuit which detects that the phases of two signals are in agreement. The digital PLL circuit stops a phase adjustment operation, while the phases of two signals are in agreement. As a result, deterioration of the phase adjustment capability due to the low power consumption does not arise.
(Patent Document 1) Japanese Unexamined Patent Publication No. 2008-160594
(Patent Document 2) Japanese Unexamined Patent Publication No. Hei 11(1999)-127062
(Patent Document 3) Japanese Unexamined Patent Publication No. Hei 10(1998)-070456